1. Field of the Invention
The present invention relates to an apparatus for improving data access reliability of flash memories and, more particularly, to an apparatus applicable to flash memories for improving data access reliability by hardware encoding, comparison, arbitration and decoding.
2. The Related Arts
Flash memory is widely used in computer and consumer electronic digital equipments, such as flash memory pen, MP3 player. However, the current technology for access control for the flash memory allows about 1,000,000 erases to a flash memory area. Beyond the limit, the data stored in that flash memory area may not be able to read. When an area in the flash memory cannot be read because it exceeds the erase limit, often referred as tolerance, it is sometimes referred as penetrated.
Because of the above constrain on the lifespan of the flash memory, it is an important issue to assure that the penetrated flash memory can still be read. The conventional approaches to this problem are either to improve the hardware technology, namely raising the tolerance, or to use the error correction code (ECC) to correct the errors. The capability of ECC approach is constrained by the flash memory page size and the spare area size. For example, to detect two-bit error, and correct one-bit error for a 512-byte page, it requires 24 bits of ECC.
FIG. 1 of the attached drawings shows a schematic view of a conventional structure of flash memory data access. To write data A1 into a data area A2, the access control also generates an ECC A3 to be stored in the reserved area A4 after the data area A2. When this type of data access structure is applied in the even more unreliable multi-level cell (MLC) flash memory, the problem is even more severe. This is because a cell of an MLC flash memory stores two or more bits; and therefore, the value of the bit can be erroneously determined. Although increasing the size of reserved area to provide more storage space for ECC can slightly alleviate the problem, this approach must change the entire system and hardware design of the current flash memory, which is not economically viable.
In addition, Taiwan Patent Publication No. 575806 disclosed a method for enhancing the ECC capability of flash memory and encrypting data. However, the disclosed method is not applicable to the two-bit error correction capability, and may lead to erroneous data determination.